Complete the blanks in the following question with the appropriate answer Consider the following diagram where the numbers on each gate represent the propagation delay through that gate in nanoseconds. Assuming no clock skew and nearly zero routing delay, what is the approximate maximum frequency for the clock in this example? Round your answer to the nearest whole number of MHz. 0.7 0.9 0.9 Flip Flops: clk-to-Q: 1.5 ns setup time: 0.6 ns hold time: 0.1 ns CLK> The maximum frequency is MHz