Complete the following timing diagram for the circuit from the previous problem (repeated here). Your characteristic table from the previous problem will be helpful. Remember that the flip-flops are positive edge triggered. This means that Ao and A1 will change only when the clock rises from 0 to 1. You may assume that changes propogate instantaneously (i.e. you do not need to wait a gate delay after the clock rises before updating the outputs). B-Low Lov OV A1 Clock - - - - - - - - - - - - 1.... - - - - - - - - - - - - - - - - - T