Complete the following verilog code:

module rs_latch( q, qb, r, s ); output q, qb; input r, s; //complete

endmodule

module d_latch( q, d, clk); output q; input d, clk; //complete using rs_latch

endmodule

module dff( q, d, clk); output q; input d, clk;

// complete using two d_latch

endmodule