Complete the following VHDL code to implement a divider $(\frac{A}{B})$ using the repeated subtraction method. $[$ e$.$g$.$ if $A=14$ and $B=3_{?},$ then the result can be calculated as: $14-3-3-3-3=2$

$$ The quotient $(Q)=$ number of subtractions $=4$ and the remainder $(R)=2]$

library IEEE;

use IEEE.std$\_$logic$\_1164.$all;

use IEEE.std$\_$logic$\_$unsigned.all;

entity divider is

port CLK : in std$\_$logic;

A$,$ B : in std$\_$logic$\_$vector$(3$ downto $0)$;

Q$,$ R : out std$\_$logic$\_$vector$(3$ downto $0))$;

end divider;

architecture behavioral of divider is

Your design should include the following pins:

CLK: $($positive edge trigger input clock$)$

A: The first number $(4$ bits$)$

B: The Second number $(4$ bits$)$

$Q$: The quotient $(4$ bits$)$

$R$ : The remainder $(4$ bits$)$

Notes:

Use behavioral description

DO NOT use the following operators: $/,$ MOD, REM

DO NOT use an algorithmic state machine.

The calculation should be synchronous with the clock $($the result should be calculated in a single clock cycle at the rising edge of the input clock$)$

You have to use EDA Playground for this assignment

You have to submit two files:

A VHDL code to implement your Design.

A testbench file to simulate and test your design:

a$.$ Set the clock period to be $4ns.$

b$.$ You have to cover all the possible cases for the input data $($except: B$="0000"$ and B$="1111")$

$(224$ different cases$)$

c$.$ For each case you have to:

i$.$ Select the value for A $($form $"0000"$ to $"1111")$ and the value for B $($from $"0001"$ to $"1110").$

ii$.$ Wait for two clock cycles