Complete Truth Table and Timing Diagram for each Flip Flops, all inputs are active high, clock is positive-edge triggered (rising edge) 1.1 D Flip Flop D Q 0 0 0 1.2 T Flip Flop T 1 1 0 0 0 0 1 1.3 S-R Flip Flop S RQ 0 1 0 0 1 1 0 0 1 Command Q+ 0 1 Q Command Q+ 0 1 1 0 1 * 1.4 J-K Flip Flop J K Q Command Q+ 1 0 1 0 OHO 0 1 0 1 0 1 Command Q+ 0 1 1 clock o D 1 1 Qo. T 0 clock o 1 ***** Qo- clock o. So 1 Ro Qo O clocko- 0 Ko. 0