Computer Architecture The objective of this exercise is to work through the design of a cache. Show all the details to get full credit. (a) The instruction set for your architecture has 44-bit addresses, with each addressable item being a byte. You elect to design a 4-way set-associate cache with each of the four blocks in a set containing 64 bytes. Assume that you have 256 sets in the cache. Show the hardware implementation of the cache and how the 44-bit physical address is treated in performing a cache reference. (b) Consider the following sequence of addresses (all are hex numbers). 0E1B01AA050, 0E1B01AA073, 0E1B2FE3057, 0E1B4FFD85F, 0E1B01AA04E In your cache, what will be the tags in the set that contain these references at the end of the sequence? Assume that cache is initially empty. Show the final states of the cache and determine hit ratio. (c) The cost of your cache is roughly proportional to the number of bits of storage required. The purpose of this question is to determine how many bits are used for each function. How many bits are required to hold the cache data? How many bits are required to store address tags?