1) [45] Consider a 2-way set associative cache that has 32 blocks and 16 bytes per block. Assume a 32 bit address. a) How many bits are needed to store the tag in the cache? b) For the above cache, assume LRU is used for cache replacement. Given the following address access sequence (data are shown in hexadecimal). For each memory access, identify its block offset, set index, and tag, decide whether it is a cache hit or cache miss. If it is a cache miss, also mark whether it is compulsory miss, conflict miss or capacity Address Tag Index Offset Hit/Miss? Type of miss Ox100 Ox104 Ox108 Ox200 Ox204 x410 100 Ox108 Ox40C Ox408 300 Ox284 Ox280 304 c) Calculate the miss rate for this memory access sequence. d) Assume that the cache is initially empty. After the above memory access sequence, how many cache blocks are occupied? e) If the same cache is direct mapped, how wide is the tag field?