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Consider a 3 2 - bit byte address, a direct - mapped cache of size 6 4 K bytes with each block of size four
Consider a bit byte address, a directmapped cache of size K bytes with
each block of size four words. A series of memory accesses occur as follows
assume all states are reset initially: xDFxDFC
xAAxAAxDF The hit access is
axDFC
bXAA
cXDF
dxAA
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