Consider a cache with a line size of 128 bytes. A word consists of 4 bytes from the memory (through the cache). Also assume 60% of the instructions require read operation, and 40% of the instructions require write operation. If a write-back policy is used, assume that on average 25% of the lines in the cache is dirty a. Assume there is a 3% miss rate (0.97 hit ratio) Compute the amount of main memory traffic, in terms of bytes per instruction for both write-through and write-back policies. Memory is read into cache one line at a time. However, for write, a single word can be written from cache to main memory b. Repeat part a for a 10% miss rate. Consider a cache with a line size of 128 bytes. A word consists of 4 bytes from the memory (through the cache). Also assume 60% of the instructions require read operation, and 40% of the instructions require write operation. If a write-back policy is used, assume that on average 25% of the lines in the cache is dirty a. Assume there is a 3% miss rate (0.97 hit ratio) Compute the amount of main memory traffic, in terms of bytes per instruction for both write-through and write-back policies. Memory is read into cache one line at a time. However, for write, a single word can be written from cache to main memory b. Repeat part a for a 10% miss rate