Consider a computer system with the following properties:

• Each word of memory holds the standard 1 byte (8 bits) of information.
• The computer architecture uses 24 bits to specify memory addresses and 8 bits for the opcode.
• The memory uses a single level cache, each cache line holds 512 bytes in the cache.
• The total size of the cache is 1 MB.
• The cache is a two-way set-associative cache.

Answer each of the following questions about the system:

1. What is the maximum memory size supported by this computer architecture?

2. How many cache sets are there in the cache?  (Hint: In a two-way set-associative cache, each set maps to 2 cache lines.  And you were given the total cache size, and the size of each line).

3. For a set associative cache, a memory reference is broken up into 3 fields as described by our text:

tag (s - (d+w))

set (d)

word (w)

How long is each field?  Some hints: The number of bits needed to identify the set d depends on the number of sets there are (previous question).  The word size w is a function of how big a cache line is.  And finally, the total number of bits is the same as the memory address size in bits s, so the combination of all 3 fields has to add up to the number of bits in the memory address.

4.  Assume the cache is filled with the following data:

	cache way 1			cache way 2
Line Number	Valid Bit	Tag	Data	Valid Bit	Tag	Data
...
00...00011	1	00...01	...	1	10...00	...
...
00...01000	1	10...01	...	0	00...10	...
00...01001	0	10...00	...	1	00...00	...
...

In this table, ... represents a sequence of zero(s)

Given the following memory references, identify each of them as a cache hit (write H in the blank) or a cache miss (write M in the blank).

Hints: The valid bit indicates a cache entry that is not actually valid anymore for some reason (maybe cache invalidated because of write in other core/cache for example).  So if a reference resolves to a line that is not valid, it is still a miss.  Make sure you correctly identify the line and tag when determining a hit or miss here.

Reference 1

Tag	Line	Word Offset
00...00	00...01001	1100100

Reference 2

Tag	Line	Word Offset
10...00	00...01001	0110110

Reference 3

Tag	Line	Word Offset
10...01	00...00011	1110011

Reference 4

Tag	Line	Word Offset
10...00	00...00011	0110110

Reference 5

Tag	Line	Word Offset
10...01	00...01000	0100010