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Consider a Delay locked loop with the reference clock being connected to a series of n delay elements with x as the delay per delay

Consider a Delay locked loop with the reference clock being connected to a series of n delay elements with x as the delay per delay element. It is possible to have both coarse tuning (xn close to the reference clock's period) and fine tuning (xn as a fraction of the reference clocks period) in the same Delay-Locked Loop (DLL) to achieve almost perfectly synchronized clocks.
The key is to have a control algorithm that can intelligently switch between coarse and fine tuning based on the current phase difference and the required level of synchronization accuracy. These adjustments made by the control block might involve adding or removing individual delay elements, or fine-tuning the delay of each element.
1. How can this fine tuning be achieved from the same delay elements that are also used for coarse tuning?
2. How exactly is this switch between coarse and fine tuning done by the control block? Please explain in detail.

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