Consider a Direct Mapped cache with 32-bit memory address reference byte addressable. Assume a 2 word block and a Cache size of 16 Words. Byte Addresses in Main Memory Address 64 32 92 88 256 128 96 32 96 70 80 90 Starting with an empty cache, assume the following memory address references in the corresponding order Is the underlined reference a hit or a miss in cache? Select one: a. MISS b. HIT