Consider a memory system composed of a single cache and DRAM. The parameters of the memory

system are given below:

$-$ Memory address: $16-$bit

$-$ Cache line size: $16$ bytes

$-$ Cache capacity: $64$ bytes

$-$ Set$-$associativity: $2$

$-$ Replacement policy: LRU

$-$ Write$-$back, write$-$allocate policy

$-$ Cache access latency: $4$ cycles

$-$ DRAM access latency: $100$ cycles

A$.(2$ points$)$ How many bits are required for a tag for a cache line in this cache?

B$.(3$ points$)$ What is the total storage overhead per cache line other than the tag bits if cache

coherence is not supported $($i$.$e$.,$ the cache is for a uniprocessor$).$ Examine the design

parameters carefully one by one and make sure that all the features are supported.

C$.(3$ points$)$ If MESI coherence protocol support is added to the cache, what is the minimal

amount of additional storage overhead per cache line required? Ignore the transient states

for this problem.

D$.$ Assume the cache is initially empty. Consider the following memory references given as byte

addresses where each reference is for a word$-$sized data:

$0$xDDAC, $0$x$9930,0$xA$498,0$xDDAC, $0$xF$18$C$,0$xD$5$A$4,0$x$9$A$14,0$xA$490,0$xF$18$C$,$

$0$xA$494,0$xDDA$4$

D$-$a$)(4$ points$)$ What is the cache miss rate?

D$-$b$)(2$ points$)$ What is the average memory access time in cycles?

D$-$c$)(3$ points$)$ Let n be the number of conflict misses and let m be the number of capacity

misses. What is the value of $2$n x $3$m$?$

D$-$d$)(3$ points$)$ Let n be the number of cache hits from the temporal locality and let m be the

number of cache hits from the spatial locality. What is the value of $2$n x $3$m$?$