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Consider a memory system that uses a 30-bit address to address at the byte level, plus a cache that uses a 16-byte line size. Assume
Consider a memory system that uses a 30-bit address to address at the byte level, plus a cache that uses a 16-byte line size.
Assume an fully associative cache. Show the address format of the main memory addresss.
Tag= 26-bit, Word= 4-bit | ||
Tag= 25-bit, Word= 5-bit | ||
Tag= 23-bit, Word= 7-bit | ||
Tag= 24-bit, Word= 6-bit |
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