Consider a memory system with the following parameters: - Translation Lookaside Buffer has 256 entires and it is 2-way set associative. - Page size is 4 KB. - The tag bits for TLB is 21 bits. - Physical memory is 128GB.

a) What is the virtual address size (in bits)? b) What is the physical address size (in bits)? c) How many physical pages are there? d) What is the size of virtual memory in TB? e) If the hit rate is 99% and hit time is 1 cycle to TLB, what is the average memory access time to the TBL if its miss penalty is 20 cycles when there is no page fault? f) Assume that 0.02% of the time, there is a page fault, and the disk latency is 10,000 cycles. Then, what is the average access time for TLB?