Consider a program that can execute with no stalls and a CPI of 1 if the underlying processor can service every load instruction with a 2-cycle L1 cache hit. In practice, 10% of all load instructions suffer from an L1 cache miss. Every cache miss results in a 300-cycle stall while data is fetched from memory. What is the CPI for this program if 20% of the program's instructions are load instructions?