Consider an in-order 5-stage pipeline similar to the one discussed in class, e.g., see slides 4-6 of lecture 18. First assume that the pipeline does not support bypassing (forwarding).- What are the stall cycles introduced between the folowing pairs of back-to-back instructinns? Then, sclve the same problem while assumingsup or bypassing. Clearly show your work, i.e., shaw how each instructinn goes through the 5 stages, indicate the point af production and paint of consumption, show how theonsuming instruction is held back in the D/R stage when there are stals. Rl that a register read is performed in the second half o the D/R stage and a register write is performed in the first half of the RW stage (30 points) add $4, $1, 53 2, hw $1, S2) sw $3, 8051)