Consider an instruction pipeline with 5 stages without any branch prediction: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX) and Operand Write (OW). The stage delays for IF, ID, OF, EX and OW are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns respectively.

There are intermediate storage buffers or latch after each stage and the delay of each buffer is 1 ns. A program consisting of 10 instructions I1, I2, , I10 is executed in the pipelined processor.

Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, calculate the time required to complete the program using time space table. Also identify the instruction which is not there in the pipeline when the Branch Instruction executes.