$.$ Consider individual stages of the datapath that have the following latencies:

IF ID EX MEM WB

$2\mathrm{.}0$ ns $|1\mathrm{.}5$ ns $|2\mathrm{.}5$ ns $|3\mathrm{.}0$ ns $|1\mathrm{.}0$ ns

a$.[5$ points$]$ What is the clock cycle time in a pipelined and a non$-$pipelined processor?

b$.$ Suppose the MEM stage is split into three separate stages, each with a latency of $1$ ns$.$

i$.[5$ points$]$ How many stages will the new processor have?

ii$.[5$ points$]$ What is the new clock cycle time in a pipelined and a non$-$pipelined processor?

I need help doing B$(1)$ and B$(2)$ Please show how you arrived the answers so I can understand each step