Consider individual stages of the datapath that have the following latencies: IF ID EX MEM WB 15 ns 5 ns 10 ns 30 ns 5 ns A. (5 points) What is the clock cycle time in a pipelined and non-pipelined processor? Show your work. B. (5 points) What is the total latency of an Iw (load) instruction in a pipelined and a non-pipelined processor?