Consider the 4-Stage Pipeline, what is the Speedup due to pipelining as a function of n, the number of instructions?

Repeat the question for the following. Suppose that 4-Stage Pipeline on Slide 21 have the following latencies in pico seconds: [1] FI: Fetch an instruction from memory (500 ps) [2] DA: Decode the instruction and calculate the effective address of the operand (400 ps) [3] FO: Fetch the operand (500 ps) [4] EX: Execute the operation (600 ps)