Consider the case of a multiple-bus system consisting of 50 processors, 50 memory modules, and 10 buses. Assume that a processor generates a memory request with probability r in a given cycle. Compute the bandwidth of such system for r 0.2, 0.5, and 1.0. Show also the effect on the bandwidth if the number of buses is increased to B 20, 30, and 40 for the same request probability values.