Consider the datapath shown in the diagram below. In a certain clock cycle, the following signals are active (equal to logic '1'): IdA, IdC, sel1, sel2. All other signals are not active (equal to logic ' 0 ). Which RTL operations will be carried out in this clock cycle? Select all that apply. AA+BAA+1AXA0BA+BBA+1BXB0CA+BCA+1CB