Consider the following behavior of a sequential logic. A state machine for this behavior will have one input named X$,$ one output named Z$,$ and a $2-$bit register $($using D$-$type flip$-$flops$)$ for state information. Assume that the state is represented by the Q$1$Q$0$ signals of the register. The four states are coded as follows: Q$1$Q$0=00$ means S$0$; Q$1$Q$0=01$ means S$1$; Q$1$Q$0=10$ means S$2$; and Q$1$Q$0=11$ means S$3.$