Consider the following code segment fld fld f1, 0(x1) f2, 0(x2)+ fmult.d f3, f2, f1+ fadd.d f3, f3, 1+ addi x3, x3, 1 Assume the muti-functional pipeline of Figure C.30. Show the timing diagram of this instruction sequence for the pipeline without any forwarding hardware but assuming a register read and a write in the same clock cycle.+ IF ID Integer unit EX FP/integer multiply 0000000 FP adder FP/integer divider A4 MEM WB