Consider the following instruction sequence executing on a $5-$stage

ARM pipeline with static branch prediction and branches are

resolved in the writeback stage $($i$.$e$.,$ no early resolution$).$ The

instruction sequence shown results in control hazards. $($Note that

the loop counter in R$0$ is set to $1.)$ Suppose the CPU uses a static

branch prediction policy of predict$-$always$-$untaken. How many

cycles are wasted due to control hazards?