Consider the following MIPS instructions: slti, sll, jr do the following: a. For each of the instructions above, sketch a single-cycle datapath and control unit for a MIPS processor (one sketch for each instruction) showing only whatever is needed for the relative instruction. b. Sketch a single-cycle MIPS datapath and control unit for the three instructions altogether. c. Identify the control signals needed to implement the above three instructions: RegWrite RegDst ALUSrc Branch MemWrite MemtoRe ALUOP1:0 Instruction siti sll jr Consider the following MIPS instructions: slti, sll, jr do the following: a. For each of the instructions above, sketch a single-cycle datapath and control unit for a MIPS processor (one sketch for each instruction) showing only whatever is needed for the relative instruction. b. Sketch a single-cycle MIPS datapath and control unit for the three instructions altogether. c. Identify the control signals needed to implement the above three instructions: RegWrite RegDst ALUSrc Branch MemWrite MemtoRe ALUOP1:0 Instruction siti sll jr