Consider the following RTL statements for two 4-bit registers R1 and r2.

yT₁: R2 <- R1 + R2

yT₁: R1 <- R1 + 1

Draw a diagram showing hardware implementation of the two statements. Use Fig. 4.6 for 4-bit adder, use Fig. 2.7 for registers, and use Fig. 2.4 for 4 by 1 multiplexer.