Consider the following sequence of five instructions: LD R1,0[A] ; I1 ADD R1, R1, R1 ; 12 ST 1[A], R1 ; 13 ADD R3, R2, R1 ; 14 LD R1, 2[A] ; 15 where [A], 1[A], 2[A] are memory address locations. (a) For each successive pairs of instructions above (11, 12), (12, 13), (13, 14), (14, 15), what is the type of dependency with consideration only to register RI? (4 marks) (b) In the absence of data forwarding, can each pair of successive instructions in (a) is running in a 5-stage pipeline described in Unit 3 without insertion of NOP in between the two instructions without hazard? Briefly explain what will happen to the final result using a diagram. (8 marks) (c) With reference to (a), for each instruction pair with pipeline hazard, describe how these hazards can be resolved by inserting an appropriate number of NOP instructions. (A paragraph of discussion and a diagram are expected). (5 marks) (d) Inserting NOP or stall will waste CPU cycles, name three other methods which helps to eliminate the data hazards. (3 marks)