Consider the following sequence of instructions being processed on the pipelined 5-stage RISC processor: Load R4, 16(R2): R4 destination Sub R5. R2. R3: R5 destination Store 16(R10). R5; Memory destination and R5 source Add R6, R4, R5; R6 destination Mul R8, RI, R3, R8 destination And R7, R2, R5; R7 destination Store 16(R2), R7; Memory destination and R7 source a Show the processing (assume that the pipeline does not use operand forwarding) b. Show the processing (assume that the pipeline has operand forwarding) C. Calculate CPI in both cases d. Calculate runtime (assume each clock cycle is 5ns)