Consider the following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers:

I0: ADD R3, R1, R2 I1: LOAD R6, [R3] I2: AND R7, R5, 3 I3: ADD R1, R6, R0 I4: SRL R7, R0, 8 I5: OR R2, R4, R7 I6: SUB R5, R3, R4 I7: ADD R0, R1, R10 I8: LOAD R6, [R5] I9: SUB R2, R1, R6 I10: AND R3, R7, 15

Assume the use of a four stage pipeline: fetch, decode/issue, execute, write back. Assume that all pipeline stages take one cycle except for the execute stage. For simple integer arithmetic and logical instructions, the execute stage takes one cycle, but for a LOAD from memory, five cycles are consumed in the execute stage

1) If we only have a simple scalar pipeline, but allow out-of-order execution, show the pipeline activity.

2)Repeat the above questions if we have a superscalar implementation that can handle two instructions at a time at each stage by

using in-order issue with in-order completion policy.

using in-order issue with out-of-order completion policy.

using out-of-order issue with out-of-order completion policy.