Consider the following sequence of instructions
Add #20, R0, R1
Mul #3, R2, R3
Add R4, R5, R6
Div R7, R8,R9
In all instructions. The destination operand is given last. Initially, registers R0 and R2 contains 2000 and 50, respectively. R4 and R5 contain 15 and 25, respectively. These instructions are executed in a computer that has a four-stage pipeline. Assume that the first instruction if fetched in clock cycle 1, and that instruction fetch requires only one clock cycle.
i. Draw the diagram for the above instruction. Describe the operation being performed by each pipeline stage during each of clock cycles 1 through 4.
ii. Give the result of each stage (Fetch, Decode, Execute, Write) at the end of clock cycle 4.