Consider the following statements about logic synthesis

A$.$ It involves taking a netlist and producing a layout

B$.$ It involves taking an RTL and producing a functionally equivalent netlist

C$.$ It considers given timing constraints and tries to meet it

D$.$ It characterizes standard cells and creates a timing library in Liberty format

Which of the above statements are true?

Only A

Only B

Only A and C

Only B and C

Only A$,$ C$,$ and D

Only B$,$ C$,$ and D

All A$,$ B$,$ C$,$ D