Consider the following vector code run on a 500 MHz version of VMIPS for a fixed vector length of 64. The latency of load and store unit is 12 cycles, add unit 6 cycles, multiply unit 7 cycles and divide unit 20 cycles.

LV V1, Ra

MULV.D V2, V1, V3

ADDV.D V4, V1, V3

SV Rb, V2

SV Rc, V4

a) Assuming no chaining and a single memory pipeline, determine how many clock periods it would take to run the above VMIPS vector code.

b) If the vector sequence is chained, how many clock cycles it would take to run the above vector code?

c) Suppose VMIPS had three memory pipelines and chaining. If there were no bank conflicts in the accesses for the above loop, how many clock cycles are required to run this sequence?

Question

Consider the following vector code run on a 500 MHz version of VMIPS for a fixed vector length of 64. The latency of load and store unit is 12 cycles, add unit 6 cycles, multiply unit 7 cycles and divide unit 20 cycles.

LV V1, Ra

MULV.D V2, V1, V3

ADDV.D V4, V1, V3

SV Rb, V2

SV Rc, V4

a) Assuming no chaining and a single memory pipeline, determine how many clock periods it would take to run the above VMIPS vector code.

b) If the vector sequence is chained, how many clock cycles it would take to run the above vector code?

c) Suppose VMIPS had three memory pipelines and chaining. If there were no bank conflicts in the accesses for the above loop, how many clock cycles are required to run this sequence?

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Consider the following vector code run on a 500 MHz version of VMIPS for a fixed vector length of 64. The latency of load and

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