Consider the fragment of MIPS assembly below:

sw $s5, 12($s3)

lw $s5, 8($s3)

sub $s4, $s2, $s1

beq $s4, $zero, label

add $s2, $s0, $s1

sub $s2, $s6, $s1

Suppose the pipeline was modified so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data.

1. (2 point) Draw a pipeline diagram to show where the code above will stall.
2. (1 point) In general, is it possible to reduce the number of stalls resulting from this structural hazard by reordering code?
3. (1 point) We have seen that data hazards can be eliminated by adding NOPs to the code. Can you do the same with this structural hazard? If so, explain how. If not, explain why not.
4. (1 point) Assume you could build a CPU where the clock cycle time was different for each instruction, according to the following mix.

R-type / I-type (non-lw)	lw	sw	beq
52%	25%	11%	12%

Approximately how many stalls would you expect this structural hazard would have?

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