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Consider the pipelined MIPS implementation shown in Figure 4 . 5 1 ( page 3 1 6 ) . The value of the PCSrc signal
Consider the pipelined MIPS implementation shown in Figure
page
The value of the
PCSrc signal is computed in the MEM stage. Could the PCSrc signal be computed in the EX stage
instead
If so
what would be the advantages of making this change? Also, what would be the
disadvantages of making this change? Hint: Take into account both performance and implementation
complexity considerations. Also, consider the possibility that a change may be potentially
advantageous, but the benefits actually depend on another change to also be made.
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