Consider the SDRAM timing diagram in Figure 7.19. Suppose there are four memory read cycle, as follow, where the data bus is 32 bits:

Row address x, burst size = 4, and column addresses x1 and x2 (32 B total)

Row address y, burst size = 4, and column addresses y1 and y2 (32 B total)

1. Draw the timing diagram
2. Determine memory efficiency. Ignore row deactivation time.
3. 

10. Clock Address BuStHow Data 1 cycle row activation 13 cycles) r Data I Data Out Data Data Data Out Out Out read (2 cycles) Out 2nd burst data values 1st burst data values FiGuRE 7.19 A hypothetical SDRAM access illustrating two consecutive read cycles with burst size Assume 1 clock cycle to enter a burst size, 3 clock cycles to activate a row, and 2 clock cycles to complete a read or write access