Consider the sequence of instructions shown below. Assume the instructions are pipelined under ideal conditions, i.e., assume there are no hazards so each subsequent instruction enters the pipeline in the clock cycle following the previous instruction. However, there are data hazards present, so the exercise is to document all data hazards as they exist in the ideal pipelined sequence, i.e., specify the data hazard, but do not resolve it. For each hazard:

(a) specify the involved instructions by listing the line numbers and the mnemonics of the instructions (e.g., 1 lw and 2 and);

(b) list the hazard type (e.g., type 1a, 1b, 2a, or 2b);

(c) list the two registers that are involved in the conflict;

(d) specify the stage and clock cycle number when the first instruction writes to the destination register; and

(e) specify the stage and clock cycle number when the second register would read (the old or wrong value of the register). You do not need to include the pipeline diagram in your solution.

For example, to get you started: (a) the first hazard is between instructions 1 lw and 3 addi; (b) it is a type 2a MEM hazard; (c) the conflicting registers are rt = $t0 for the lw and rs = $t0 for the addi; (d) the lw will write to $t0 in the WB stage in clock cycle 5; (e) the addi would read the old/wrong value of $t0 in the ID stage in clock cycle 4. The reason this is a MEM hazard is because lw obtains the value in the MEM stage that will be written to $t0 in lw's WB stage and that value is needed as the first source register for addi when it reaches the EX stage.

1 lw $t0, 0($sp)

2 and $t9, $t9, $t9

3 addi $t0, $t0, 1

4 sub $t1, $t2, $t0

5 or $t1, $t1, $t0

6 andi $t1, $t1, 0x80