Consider the sequential circuit implementing serial addition built with two shift registers, a 1-bit full adder and a D flip-flop (Figure 6.5 in Morris Mano & Michael Ciletti, Digital Design). Design and implement in Verilog a 4-bit version of this circuit. Use the behavioral implementation behavioral_serial_adder.vl and make the following changes/additions: 1. Create a logic diagram of the circuit. Use Figure 6.5 and update it using the structure of the behavioral model (add a 2x1 multiplexer and parallel inputs to the shift registers). and also Create a logic diagram of the shift register with parallel load as implemented in module shiftreg (block level multiplexers and D-flip-flops). Implement modules shiftreg and serial_adder at gate-level using gate-level D-flip-flops, full adder, and 2x1 multiplexers (http://www.cs.ccsu.edu/~markov/ccsu_courses/354Syllabus.html#Synchronous). And test the circuit with several inputs (adding positive and negative numbers) and show the output. And in the end Write a report, including the logic diagrams, the Verilog source code and the test results. The report must include your name.