Construct traffic controller state table, state machine diagram, and schematic circuit design.

The intent of this project is to produce a design for a traffic light controller using Verilog hardware description language (HDL). This traffic controller will be modeled as a state machine and will control the traffic lights at the four-way intersection shown in the diagram below:

Figure 1: Four-way intersection with traffic lights

In the project instructions , the intersection is described as consisting of a busy highway and an infrequently traveled farm road. The traffic controller design is to account for this use difference, with highway traffic taking precedence over farm road traffic (e.g. the highway will have the green light at all times when no traffic is present on the farm road). In addition to this general design principle, the project specifications include five requirements the light controller must meet in order to be considered acceptable for the application

When the light is green on A Street and a car is waiting on B Street, give A Street a yellow light for one clock cycle and then give A Street a red light and B Street a green light for at least two cycles.

When the light is green on A Street and there is no car on B Street, leave the light green on A Street.

When the is green on B Street (and weve finished the two cycles from step 1) and a car is waiting on A Street, give B Street a yellow light for one clock cycle and then give B Street a red light and A Street a green light for at least two cycles.

When the light is green on B Street and there is no car on A Street, leave the light green on B Street.

When you press the reset switch, after no more than six cycles, the light should be initially green on A Street and red on B Street and the controller should be ready for operation.