Could any one write the verilog code in cmos and pmos for this circuit """ Design a CMOS circuit with four input and one output. The output is 1 when the binary value of inputs is less than 3 and greater than 10. The output is 0 otherwise."""

please pleassse :(

I write this but I dont know how to write the test

In cmos and pmos

?input4.v module in4(A.B. C. D. Y); input A, B.C.D output Y assign Y= (A&B) | ("A&NB&~C) endmodule | (~A&NB&C&ND) l (A&C&D); ?input4.v module in4(A.B. C. D. Y); input A, B.C.D output Y assign Y= (A&B) | ("A&NB&~C) endmodule | (~A&NB&C&ND) l (A&C&D)