Create a new Vivado Project. Select the XC7A10OT-1CSG324 Artix-7 FPGA device. Write the VHDL code for the given circuit. Suggestion: create a separate file for modulo-6 counter, shift Register, shift register with sclr input, register, adder, hex to 7-segments decoder, FSM, and top file. Write the VHDL testbench (you must generate a 100 MHz input clock for your simulations) to test the following cases: DataA# 100111 (39), DataB 0110 (6) DataA-110101 (53), DataB- 1101 (13) DataA-100101 (37), DataB 1111 (15) DataA-010011 (19), DataB 0100 (4) DataA-110011 (51), DataB0010 (2) a DataA-011101 (29), DataB 1001 (7) and Timing Simulation of your design. Demonstrate this to your TA I/O Assignment: Create the XDC file. Nexys-4-DDR: Use SWO to SW10 for the inputs, CLK100MHZ for the input clock CPU RESET push-button for resetn, a LED for 'done, six LEDs for Q, and the 7-segment display for R Generate and download the bitstream on the FPGA and test. Demonstrate this to your TA Create a new Vivado Project. Select the XC7A10OT-1CSG324 Artix-7 FPGA device. Write the VHDL code for the given circuit. Suggestion: create a separate file for modulo-6 counter, shift Register, shift register with sclr input, register, adder, hex to 7-segments decoder, FSM, and top file. Write the VHDL testbench (you must generate a 100 MHz input clock for your simulations) to test the following cases: DataA# 100111 (39), DataB 0110 (6) DataA-110101 (53), DataB- 1101 (13) DataA-100101 (37), DataB 1111 (15) DataA-010011 (19), DataB 0100 (4) DataA-110011 (51), DataB0010 (2) a DataA-011101 (29), DataB 1001 (7) and Timing Simulation of your design. Demonstrate this to your TA I/O Assignment: Create the XDC file. Nexys-4-DDR: Use SWO to SW10 for the inputs, CLK100MHZ for the input clock CPU RESET push-button for resetn, a LED for 'done, six LEDs for Q, and the 7-segment display for R Generate and download the bitstream on the FPGA and test. Demonstrate this to your TA