cse$120\_$spring

For the following questions, it v

Mq$1$M$2$VXwmNNzQoxs$8$SjR$8$sfAR$/$edit

Calibri

$11$

$11$

B

I

U

A

harr

$2$

$3$

$4$

$5$

$6$

$1.$

$2$

$3$

$4$

initialized to $20.$ Other registers, if un$-$initialized, can be assumed to be $0$ by default.

fdxmw

fdxmw

A$)(5$pts$)$ Suppose you executed the code below on a pipelined system that

does not handle data hazards.

Also, the register file does not have the feature of reading and writing in the same clock cycle. For example, if the old value of $x1$ is $10.$ Now, let's assume that in Clock Cycle $5($CC$5),$ we are bot writing a new value of $20$ to $x1$ and also reading $1$ in the same clock cycle. Then, the output value from the read would be $10,$ NOT $20.$ This new value of $20$ will be available in $x1$ only from the next clock cycle CC$6.$

In this context, what will be the final values of registers $x13,x14,$ and $x15$ at the end of this code block?

$I1$: addi $x13,x11,1$

$I2$: add $x14,x0,x12$

$I3$: xor $x15,x11,x12$

$I4$: sub $x13,x15,x14$

$I5$: add $x14,x15,x13$