Currently if you compile and run the program with test.asm as following, its output shows that only ADD instruction can be assembled, decoded and disassembled. For other instructions, \"Unrecognized instruction...\" message is printed out. yanyh@vm:/csce212_simcpu$ gcc assembler_decoder.c -o assembler_decoder yanyh@vm:~/csce212_simcpu$ ./assembler_decoder test.asm ADDI, $s3, $S0, 1 # instruction #0, i- 1; # instruction #1, Init N 256 # instruction #2, $s4 has 255 # 3, Jump to the end of the code, use relative address 12 Unrecognized instruction: ADDI, ignore. Unrecognized instruction: ADDI, ignore. Unrecognized instruction: ADDI, ignore. Unrecognized instruction: BEQ, ignore. 0x00635800: ADD, $s11, $S3, $S3 0x016b5800: ADD, $s11, $s11, $s11 0x01622800: ADD, $S5, $s11, $S2 Unrecognized instruction: LW, ignore. Unrecognized instruction: LW, ignore. Unrecognized instruction: LW, ignore. 0x00c74800: ADD, $S9, $s6, $S7 0x01094800: ADD, $s9, $s8, $S9 0x01615000: ADD, $S10, $s11, $S1 Unrecognized instruction: SW, ignore. Unrecognized instruction: ADDI, ignore. Unrecognized instruction: J, ignore. ADDI, $s4, $s0, 256 ADDI, $s4, $S4, -2 BEQ, $S3, $S4, 12 ADD, $s11, $S3, $S3 ADD, $s11, $s11, $s11 ADD, $S5, $s11, $S2 LW $S6, $S5, -4 LW, $S7, $S5, 0 LW, $s8, $s5, 4 ADD, $S9, $S6, $S7 ADD, $S9, $S8, $S9 ADD, $s10, $s11, $s1 SW, $S9, $S10, 0 ADDI, $S3, $S3, 1 J, 3 i = 1*2*2, now $s11 has &B[i] is now in $s5 B[i-1] is now in $s6 B[i] is now in $57 B[i+1] is now in $58 B[i-1] + B[i] # 5, # 6, # 7, # 8, # 9, # 10, i#4 # 12, &A [i] is now in $s10 # 13, A[i] stored the result # 14, i++ # 15, Jump instruction #3 (BEQ instruction, use absolute address) After your implementation, your program should output the same or similar output as in the following screenshot using the test.asm file as input. Your program will be evaluated using another example program when being graded. Your submission needs to include your source code and the screenshot of your execution (similar to mine). yanyh@vm:~/csce212_simcpu$ /assembler_decoder test.asm ADDI, $s3, $s0, 1 ADDI, $s4, $s0, 256 ADDI, $s4, $S4, -2 BEQ, $S3, $S4, 12 ADD, $S11, $S3, $S3 ADD, $s11, $S11, $s11 ADD, $S5, $s11, $s2 LW, $S6, $S5, -4 LW, $S7, $S5, 0 LW, $s8, $S5, 4 ADD, $S9, $s6, $S7 ADD, $S9, $s8, $s9 ADD, $s10, $s11, $s1 SW, $$9, $S10, 0 ADDI, $s3, $$3, 1 J, 3 # instruction #0, i 1; # instruction #1, Init N 256 # instruction #2, $54 has 255 # 3, Jump to the end of the code, use relative address 12 # 4, i=1*2 # 5, i = i*2*2, now $s11 has i*4 # 6, &B[i] is now in $s5 # 7, B[1-1] is now in $s6 # 8, B[i] is now in $57 # 9, B[i+1] is now in $s8 # 10, B[i-1] + B[i] 0x14030001: ADDI, $S3, $S0, 1 0x14040100: ADDI, $S4, $s0, 256 0x1484fffe: ADDI, $S4, $S4, -2 0x3083000c: BEQ, $S3, $S4, 12 0x00635800: ADD, $s11, $S3, $S3 0x016b5800: ADD, $s11, $s11, $S11 0x01622800: ADD, $s5, $s11, $S2 0x20a6fffc: LW, $s6, $s5, -4 0x20a70000: LW, $S7, $s5, 0 0x20a80004: LW, $S8, $S5, 4 0x00c74800: ADD, $s9, $s6, $s7 0x01094800: ADD, $s9, $S8, $s9 0x01615000: ADD, $S10, $s11, $S1 0x25490000: SW, $S9, $s10, 0 0x14630001: ADDI, $S3, $S3, 1 0x3c000003: J, 3 # 12, &A [i] is now in $s10 # 13, A[i] stored the result # 14, i++ # 15, Jump instruction #3 (BEQ instruction, use absolute address) Instruction [25-0ShiftJ 25-0, JTlmm2 eft 2 ump address 131-0] PCnext 26 28 0 Add LI PC+4 Add result BTaddrPC+40rBTaddr Shift left 2 RegDst Jum MemRead Instruction (31-26 C INS31-26, Func MemtoFR MemWrite RegWrite Control ALU PC PCnekt Instruction [25-21 Read PCRead INS25-21, RSselectregister 1 Read RSvalue, ALU Instruction [20-16Read address data 1 Instruction lNS20-16, RTselect register 2 MEMout ALUout 31-0 MWrite2 Instruction |||Instruction [15-11] gister data 2 ALUin2 result +Address Rea ul memory INS15-11, RDselectWrite data Registers Write Data data memory RWselect RTvalue, MEM 16 Sign- extend 32 Instruction [15-0) INS15-0, Imm ALU control ALUout ignore Instruction [5-0] RWvalue ignore FIGURE 4.24 The simple control and datapath are extended to handle the jump instruction. An additional multiplexor (at 2. CPU Functional Simulator The second component of the project is to create a functional simulator of CPU of the above diagram using a program. In the program, CPU components (instruction memory, registers, ALU, and data memory), datapath, control signal and logic in the CPU diagram are implemented in the source code to support the designed 7 instructions?