D 7.5 Design the circuit in Fig. P7.5 to obtain a dc voltage of +0.2V at...

Transcribed Image Text:

D 7.5 Design the circuit in Fig. P7.5 to obtain a dc voltage of +0.2V at each of the drains of Q and Q when VG1 = G2 = 0 V. Operate all transistors at Voy = 0.2 V and assume that for the process technology in which the cir- cuit is fabricated, V = 0.5 V and Cox = 250 A/V. Neglect channel-length modulation. Determine the values of R, RD, and the W/L ratios of Q1, Q2, 23, and Q4. What is the input common-mode voltage range for your design? VDD = +1.2 V +1.2 V 0.1 mA R 24 Figure P7.5 Rp RD VG2 UGI Q2 Q1 O -Vss=-1.2 V 0.4 mA 23 D 7.5 Design the circuit in Fig. P7.5 to obtain a dc voltage of +0.2V at each of the drains of Q and Q when VG1 = G2 = 0 V. Operate all transistors at Voy = 0.2 V and assume that for the process technology in which the cir- cuit is fabricated, V = 0.5 V and Cox = 250 A/V. Neglect channel-length modulation. Determine the values of R, RD, and the W/L ratios of Q1, Q2, 23, and Q4. What is the input common-mode voltage range for your design? VDD = +1.2 V +1.2 V 0.1 mA R 24 Figure P7.5 Rp RD VG2 UGI Q2 Q1 O -Vss=-1.2 V 0.4 mA 23