Obtain the Verilog model for the 4-bit counter with preset with account for the propagation delays from CLOCK to Q and CLOCK to TC from the datasheet for 74HC161. Verify the model: obtain waveforms for Q, TC with PE_ stimulated to operate with preset to a state of your choice following by counting to 1111. Obtain the Verilog model for the 6-bit shift register with asynchronous CLEAR taking into account the propagation delay from D to Q and the setup time for 74HC174. Verify the register operation: obtain the waveforms for parallel outputs after clearing and serial-in=1, observe the data shift. Obtain the SPI Master schematic using the modules above as building blocks. Obtain the waveforms for all Master signals for a complete acquisition of 9 bits from the ADC. Sketch the IC pinouts (74HC161, 74HC174, 74HC02) and show pin wiring connections.