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Data 2 2 2 to ( 2 2 2 + 2 2 5 ) - 1 6 . Why can the instruction memory and the

Data 222 to (222+225)-1
6. Why can the instruction memory and the data memory share the same address bus in Cortex-M3, Cortex-M4 and Cortex-M7? In other words, why can we put the instruction memory and the data memory in the same memory address space (i.e. Unified address space within Harvard architecture)?
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