Description: Build and test the following circuits using gate-level modeling in Verilog HDL.

1. 3-input minority function. Returns 1 if the number of 1s in the input is less than the number of 0s, otherwise returns 0.

2. Conditional 2-bit inverter. Takes three inputs x, y, and z and returns two outputs A and B. If x=0 then A=y and B=z, if x=1 then A=y' and B=z'. Don't use XOR gates for the implementation.

3 . 1-bit full adder by cascading two half adders. Create a separate module for the half adder.

4. 1-bit full adder direct implementation. Derive the output functions from the truth table and use 2-level NAND logic for the implementation.

5. 4-bit adder/subtractor with overflow detection by cascading four 1-bit full adders. Use multiple bit variables (vectors) for the inputs and output (see 4-bit-adder.vl) .

Requirements:

1. Create truth tables and use maps for simplification (not needed for circuits 3 and 5).
2. Create a module for each circuit, instantiate it in a test module and test it.
3. The hierarchical circuits (3 and 5) should use instances of their constituent modules.
4. For testing use all combinations of input values and show the corresponding output for all circuits except for the 4-bit adder/subtractor.
5. For testing the 4-bit adder/subtractor pick one positive and one negative number and add and subtract all combinations of them. Test also overflow situations for both add and subtract. Show the inputs/output both in binary and signed decimal.

Documentation:

Write a project report containing for each circuit:

1. Short text description.
2. Truth tables and maps for circuts 1, 2, and 4 (not needed for the hierarchical circuits 3 and 5).
3. Gate level circuit diagram with components and wires labeled with the module and variable names used in the Verilog code. Use block diagrams for the components of the hierarchical circuits 3 and 5.
4. Verilog source code (included as text, not image).
5. Verilog output showing the test results as explained in the requirements.