Design a 16 bit one-level carry bypass adder using dynamic Manchester carry chain. The adder has 33 inputs: A0~A15, B0 B15, and CLK. It has 17 outputs: S0 S16. Please stick with this naming convention in your design so that later you can verify its functionality using the given test bench. Each bypass group has four-bit slice. Each bit slice should be laid out horizontally. Implement the layout using Cadence Virtuoso layout editor. Verify the function using HSPICE (The detailed information is provided in an example given in Lecture 18) and find out the worst case delay Your report should include the following discussions: 1. How many different bit slices are there in the adder? How to reuse the design of some bit slice to reduce the design time? 2. Draw the gate level schematic of each unique bit slice 3. How many different gates (library cells) are there? Draw the transistor level schematic for each gate. 4. For each bit slice, how to place the gates so that the length of interconnect can be How to determine the height of each row? Which input vector will give the worst case delay? Find out the delay using HSPICE and record it in your report. 5. 6. 7. Special requirement: use the transmission gate implementation for your XOR gate 8. Extra credit: Provide the simulation waveform which could prove that your adder is truly a carry bypass adder. Design a 16 bit one-level carry bypass adder using dynamic Manchester carry chain. The adder has 33 inputs: A0~A15, B0 B15, and CLK. It has 17 outputs: S0 S16. Please stick with this naming convention in your design so that later you can verify its functionality using the given test bench. Each bypass group has four-bit slice. Each bit slice should be laid out horizontally. Implement the layout using Cadence Virtuoso layout editor. Verify the function using HSPICE (The detailed information is provided in an example given in Lecture 18) and find out the worst case delay Your report should include the following discussions: 1. How many different bit slices are there in the adder? How to reuse the design of some bit slice to reduce the design time? 2. Draw the gate level schematic of each unique bit slice 3. How many different gates (library cells) are there? Draw the transistor level schematic for each gate. 4. For each bit slice, how to place the gates so that the length of interconnect can be How to determine the height of each row? Which input vector will give the worst case delay? Find out the delay using HSPICE and record it in your report. 5. 6. 7. Special requirement: use the transmission gate implementation for your XOR gate 8. Extra credit: Provide the simulation waveform which could prove that your adder is truly a carry bypass adder
