Design a $2-$bit, cyclic binary up$-$counter and use it to implement a circuit that generates continuously the sequence $0111$ and displays it by the output OUT $($the

leftmost bit of the sequence is generated when the counter is in the initial state $00).$ The counter increases by $1$ at every positive edge of the clock signal.The final

circuit will have the following inputs and outputs $($use exactly these names for inputs and outputs$)$:

clk: Input. Clock signal.

RST: Reset signal. When RST $=1$ the counter is reset to $00.$

OUT: Output.

Note $1$: All flip flops must be synchronized by the $"$clk$"$ signal $($For experts: do not use "ripple$-$counter" or similar architectures$)$

Note $2$: To properly verify the circuit, VerilUOC$\_$Desktop requires all inputs of the flip flops are connected to some value. So$,$ it is necessary to connect $"$S$"$ inputs to $0$

and "load" inputs to $1.$ To do so$,$ click in "Wiring" $($left menu$),$ select "Constant" and connect the constant $($a logical $1)$ to the "load" inputs. Repeat the process and, in

the Value property of the left menu, replace the $01$ by $00($this will set the constant to $0).$ Connect the resulting constant to the $"S"$ inputs.